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DescriptionQ1042
Q1042DVDesignASIC interview problem

Drive a multi-beat ready/valid transaction

TechniquesUVMDriverBurstBackpressure
DifficultyMedium
TopicUVM Components
LanguageSystemVerilog
Requirements5 checkpoints
01

Problem

Expand one logical sequence item containing a queue of data beats into a ready/valid burst. Support backpressure, an accurate last flag, and optional idle bubbles between accepted beats.

Example input and output

Use this case to check your interpretation
Input
logical item beats=[A,B]; A handshakes; insert one idle bubble; present B with ready=0 then ready=1
Output
accepted burst=A then B; last=0 on A and last=1 held with B through its stall; item_done once
Explanation

The beat index advances only on handshakes, and an optional bubble occurs before valid is reasserted for the final beat.

02

Requirements (5)

  • Do not advance the beat index until the current beat handshakes.
  • Assert last only for the final beat and hold it stable with the data while stalled.
  • Insert a bubble only while valid is low; never ignore a possible handshake after asserting valid.
  • Call item_done() once for the complete logical transaction, not once per physical beat.
  • Reject an empty beat queue as an invalid burst item.