1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ399

Q399DesignDVNVIDIAASIC interview problem

Cross a request between powered voltage domains

TechniquesDesignDVCDCLevel shiftingIsolation

DifficultyHard

TopicLow-Power Design

LanguageSystemVerilog

Requirements4 checkpoints

Problem

Design a reliable request crossing from a switchable 0.8 V domain A to an always-on 1.0 V domain B with unrelated clocks. A may power down only after every accepted request is acknowledged.

Starting declarationSystemVerilog

// A: a_clk, a_rst_n, a_power_good, a_req, a_req_ready
// B: b_clk, b_rst_n, b_req_pulse
// Internal request and acknowledge levels cross in opposite directions.

Example input and output

Use this case to check your interpretation

Input

A accepts one request, then the power controller asks A to shut down before B acknowledges

Output

Shutdown waits; B receives one pulse; acknowledgment returns; request drops; only then may isolation and power-off occur

Explanation

The held level handshake prevents pulse loss and gives power control a definite idle state.

Requirements (4)

Use a four-phase request/acknowledge level handshake and generate exactly one B-domain pulse per accepted request.
Level-shift A-to-B and clamp the request to inactive before A powers off.
Block shutdown until the handshake is idle; keep ready low during power loss and recovery.
Synchronize both crossing levels and constrain unrelated clocks appropriately while preserving CDC-specific checks.