DescriptionQ802
Q802DesignDVNVIDIAASIC interview problem
Design glitch-free clock gating
TechniquesDesignDVClock gatingICGAssertions
DifficultyMedium
TopicLow-Power Design
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
Describe a glitch-free positive-edge clock-gating implementation and the checks that prove it cannot create runt pulses.
Starting declarationSystemVerilog
input logic clk, rst_n, en;
output logic gclk;Example input and output
Use this case to check your interpretationInput
en falls while clk is high and the current gclk pulse is activeOutput
The active gclk pulse completes; gating stops at the next safe low phaseExplanation
The stored gate enable cannot change during the propagated high pulse.
02
Requirements (4)
- Capture the functional enable only while clk is low, using an approved ICG or an equivalent low-phase model.
- Allow a propagated high pulse to complete even if en changes while clk is high.
- Treat reset/test disable through the library-approved safe control path; do not asynchronously truncate gclk high.
- Check source-edge alignment, pulse width, enable stability during high phase, and no gated edge while disabled.