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DescriptionQ700
Q700DVDesignASIC interview problem

Turn an APB3 agent into reusable verification IP

TechniquesAPB3UVMWait statesProtocol assertions
DifficultyHard
TopicUVM Components
LanguageSystemVerilog
Requirements4 checkpoints
01

Problem

Upgrade an active-only Advanced Peripheral Bus 3 (APB3) master agent into reusable active/passive verification IP (VIP) with wait-state handling, checking, assertions, and coverage.

Starting declarationSystemVerilog
PCLK, PRESETn, PSEL, PENABLE, PREADY;
PADDR, PWRITE, PWDATA, PRDATA, PSLVERR;

Example input and output

Use this case to check your interpretation
Input
APB read with three PREADY-low wait cycles followed by one PREADY-high ACCESS cycle
Output
one observed read; stable address/control through all waits; PRDATA sampled on completion
Explanation

Elapsed ACCESS cycles do not create extra transactions; the monitor publishes only the completed handshake.

02

Requirements (4)

  • Always create the monitor; create driver and sequencer only in active mode.
  • Drive one SETUP cycle, then ACCESS, holding address/control/data stable while PREADY is low.
  • Publish a fresh observed transaction only on PSEL && PENABLE && PREADY.
  • Check progression and stability; cover direction, waits, error, address region, and back-to-back transfers.