DescriptionQ381
Q381DVASIC interview problem
Coordinate two sequencers with a virtual sequence
TechniquesUVMVirtual sequenceParallel stimulusReset
DifficultyHard
TopicUVM Components
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
Coordinate register programming, configuration completion, parallel packet and status traffic, and a reset that may interrupt the scenario.
Starting declarationSystemVerilog
reg_sequencer reg_seqr;
packet_sequencer pkt_seqr;
reset_sequencer rst_seqr;Example input and output
Use this case to check your interpretationInput
register configuration completes; packet and status children start; reset completes firstOutput
traffic children stop, expected responses flush by policy, and unrelated testbench processes continueExplanation
The named scenario scope and explicit child handles limit cancellation to work owned by this virtual sequence.
02
Requirements (4)
- Factory-create every child sequence.
- Use typed handles to compatible sequencers.
- Express required ordering and deliberate parallelism explicitly.
- Confine reset cleanup to the scenario and define scoreboard/response flushing.