1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ741

Q741DVDesignASIC interview problem

Design a four-request arbiter verification environment

TechniquesUVMReference modelAssertionsCoverage

DifficultyHard

TopicArbiters

LanguageSystemVerilog

Requirements4 checkpoints

Problem

Design end-to-end verification for four one-cycle request inputs where simultaneous requests use lower-index priority and grants are ordered, one-hot, and held for 1 through 10 cycles.

Starting declarationSystemVerilog

input logic clk, rst_n;
input logic [3:0] req;
input logic [3:0] grant;

Example input and output

Use this case to check your interpretation

Input

req = 4'b1010 together; then grant = 4'b0010 for four cycles

Output

enqueue requester 1 then requester 3; complete one legal service for requester 1

Explanation

Low-index priority defines the model's insertion order, and the one-hot grant matches the queue front for an allowed duration.

Requirements (4)

Define how simultaneous request bits enter the pending model.
Separate driver, passive monitor, scoreboard, assertions, and coverage responsibilities.
Check one-hot grant, a pending requester, stable service, and duration 1 through 10.
Cover requesters, multi-hot arrivals, wait latency, service duration, and back-to-back grants.