1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ820

Q820DVDesignASIC interview problem

Plan verification for an asynchronous FIFO

TechniquesDVCDCAsynchronous FIFOScoreboardCoverageReset

DifficultyMedium

TopicCDC Verification

LanguageSystemVerilog

Requirements4 checkpoints

Problem

Create a concise verification plan for an eight-entry asynchronous FIFO with independent clocks and specification-defined synchronization latency on full and empty.

Starting declarationSystemVerilog

wr_clk, wr_rst_n, wr_en, wr_data, full
rd_clk, rd_rst_n, rd_en, rd_data, empty

Example input and output

Use this case to check your interpretation

Input

wr_clk runs 3x faster than rd_clk with randomized relative phase and sustained legal traffic

Output

Every accepted read matches the oldest accepted write; no loss, duplication, or reordering occurs

Explanation

The scoreboard uses acceptance conditions in each domain rather than attempted operations, so permitted flag-synchronization latency does not create false failures.

Requirements (4)

Exercise assertion and release of reset in both domains, including reset while data is stored.
Sweep clock ratios, relative phase, and drifting phase.
Model only accepted writes and reads, and compare read data in order.
Cover empty/full boundaries, pointer wrap, simultaneous activity, overflow attempts, and underflow attempts.