1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ648

Q648DVASIC interview problem

Constrain a nonzero 32-bit power of two

TechniquesDVSystemVerilogConstraintsPower of twoBit manipulation

DifficultyEasy

TopicConstrained Random

LanguageSystemVerilog

Requirements4 checkpoints

Problem

Write a solver-friendly SystemVerilog constraint for a 32-bit randomized field that contains exactly one set bit and therefore represents a nonzero power of two.

Class declarationSystemVerilog

class one_hot_value;
  rand bit [31:0] value;
endclass

Example input and output

Use this case to check your interpretation

Input

value=32'h0001_0000

Output

legal: $countones(value) = 1

Explanation

Exactly bit 16 is set, so $countones(value) equals one.

Requirements (4)

Allow every value from 32'h0000_0001 through 32'h8000_0000 that has one set bit.
Reject zero.
Reject values with two or more set bits.
Express the condition as an integral constraint without post_randomize repair.