1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

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DescriptionQ128

Q128DVDesignASIC interview problem

Vacuity

TechniquesSystemVerilogAdvanced assertions

DifficultyHard

TopicTemporal Checks

LanguageSystemVerilog

Format4 choices

An assertion has passed for the entire test, but req was never asserted. Which addition most directly exposes this vacuous-success hole?

Starting declarationSystemVerilog

assert property (@(posedge clk) req |-> ##[1:3] ack);