DescriptionQ049
Q049DVDesignASIC interview problem
Concurrent assertion scheduling
TechniquesSystemVerilogScheduling regions
DifficultyMedium
TopicSystemVerilog
LanguageSystemVerilog
Format4 choices
01
Problem
At a clock event, where are values used by a concurrent assertion normally sampled and where is the property evaluated?
Starting declarationSystemVerilog
assert property (@(posedge clk) req |-> gnt);02