DescriptionQ892
Q892DesignDVAppleASIC interview problem
Implement a synchronous FIFO with exact boundary behavior
TechniquesDesignDVFIFOReady-validBackpressure
DifficultyMedium
TopicRTL Design
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
Implement a depth-8, 32-bit synchronous FIFO. Define behavior when empty or full and make simultaneous reads and writes work correctly, including an exchange while full.
Module declarationSystemVerilog
module sync_fifo (
input logic clk, rst_n,
input logic wr_valid,
input logic [31:0] wr_data,
output logic wr_ready,
output logic rd_valid,
output logic [31:0] rd_data,
input logic rd_ready,
output logic full, empty
);Example input and output
Use this case to check your interpretationInput
Write A..H to fill the FIFO. Then drive wr_valid=1 with I and rd_ready=1 for one cycle. Later drain all entries.Output
The exchange cycle consumes A and accepts I with count still 8. Remaining read order is B,C,D,E,F,G,H,I.Explanation
Read and write fires are independent. Their simultaneous count effects cancel, while both pointers advance exactly once.
02
Requirements (4)
- Accept a write only on wr_valid && wr_ready and a read only on rd_valid && rd_ready.
- At full, allow a write in the same cycle as a read; the old head is read, the new item is written at the tail, and occupancy remains eight.
- At empty, a simultaneous wr_valid and rd_ready accepts only the write; no same-cycle empty bypass is provided, and rd_valid rises afterward.
- Preserve order, keep rd_data stable while rd_valid && !rd_ready, and make rejected full writes or empty reads have no effect.