1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

Question bank1050 results

Search questions

Filter by difficultyFilter by topicFilter by targeted interviewFilter by disciplineFilter by progress

DescriptionQ731

Q731DVDesignASIC interview problem

4-state equality

TechniquesSystemVerilogTypes and resolution

DifficultyEasy

TopicSystemVerilog

LanguageSystemVerilog

Format4 choices

What does the display print?

Starting declarationSystemVerilog

logic [1:0] a = 2'bx1;
logic [1:0] b = 2'bx1;
initial $display("%0b %0b", a == b, a === b);