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DescriptionQ598
Q598DVDesignASIC interview problem

Clocking blocks

TechniquesSystemVerilogInterfaces and timing
DifficultyMedium
TopicVerification Utilities
LanguageSystemVerilog
Format4 choices
01

Problem

What timing intent is expressed by this clocking block?

Starting declarationSystemVerilog
clocking cb @(posedge clk);
  default input #1step output #0;
  input  q;
  output d;
endclocking
02

Answer choices (4)