1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ005

Q005DesignDVASIC interview problem

Synchronize reset release in each clock domain

TechniquesResetAsync assertSync deassertRecovery/removal

DifficultyEasy

TopicReset Design

LanguageSystemVerilog

Requirements4 checkpoints

Problem

Design an active-low reset conditioner that asserts immediately but releases only after two clean destination-clock edges. Explain when synchronous and asynchronous reset styles are appropriate.

Example input and output

Use this case to check your interpretation

Input

async_reset_n falls between clocks, then rises 1 ns before a destination edge

Output

reset_out asserts immediately and deasserts only after two clean destination-clock edges

Explanation

Asynchronous assertion protects the domain immediately, while synchronized release prevents recovery/removal violations at the state elements.

Requirements (4)

Asserting arst_n low must force srst_n low without waiting for a clock.
Deassertion must pass through two flops in the destination domain.
Instantiate one conditioner per unrelated clock domain.
Do not claim that every datapath register must be reset; reset control and validity state according to the specification.