1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ458

Q458DVDesignASIC interview problem

Drive a ready/valid interface correctly

TechniquesUVMDriverReady/validBackpressure

DifficultyMedium

TopicUVM Components

LanguageSystemVerilog

Requirements4 checkpoints

Problem

Implement the core of a UVM driver for a single-beat ready/valid interface. Present one sequence item, hold its payload stable while stalled, and finish the item only after a real handshake.

Example input and output

Use this case to check your interpretation

Input

driver owns payload A; sampled ready values on successive clocks are X,0,1

Output

report unknown ready; hold valid/data A; then complete exactly one handshake on the third edge

Explanation

Only known-high ready accepts the beat; X and zero both preserve the same asserted payload and defer item_done().

Requirements (4)

A beat completes only on a sampled clock edge where valid and ready are both exactly 1.
Once valid is asserted, data and control must not change until that handshake.
Treat X or Z on ready as not-ready and report it instead of accepting the beat.
Leave the interface idle between items unless a separate pipelining policy says otherwise.