1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ434

Q434DesignDVASIC interview problem

Absorb ready/valid backpressure with a skid buffer

TechniquesSkid bufferReady/validBackpressureElastic pipeline

DifficultyHard

TopicRTL Design

LanguageSystemVerilog

Requirements4 checkpoints

Problem

Design a two-entry ready/valid skid buffer that can accept one extra item after downstream stalls, keeps output data stable while stalled, and removes the combinational ready path from downstream to upstream.

Example input and output

Use this case to check your interpretation

Input

start with occupancy=1 and front=A
cycle 1: s_valid=1,B; m_ready=0
cycle 2: s_valid=1,C; m_ready=1 (buffer is full)
cycle 3: s_valid=1,C; m_ready=1

Output

cycle 1: B is accepted into the second slot; output A stays stable; occupancy=2
cycle 2: A retires, s_ready=0 so C is not accepted; occupancy=1
cycle 3: B retires and C is accepted; occupancy remains 1

Explanation

The second slot captures B after the stall. Because ready is registered from occupancy, a pop observed while full cannot simultaneously admit C on cycle 2.

Requirements (4)

Accept input only on s_valid && s_ready and retire output only on m_valid && m_ready.
Preserve ordering across push-only, pop-only, and simultaneous push/pop cycles.
Drive s_ready from registered occupancy rather than combinationally from m_ready; when already full, a newly observed pop cannot also accept a replacement that edge.
When m_valid is high and m_ready is low, hold m_valid and m_data stable.