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DescriptionQ317
Q317DVDesignASIC interview problem

Interface modports

TechniquesSystemVerilogInterfaces and timing
DifficultyMedium
TopicVerification Utilities
LanguageSystemVerilog
Format4 choices
01

Problem

Which modport declarations correctly describe a master that drives req and observes gnt, and a slave with the opposite roles?

Interface declarationSystemVerilog
interface bus_if; logic req, gnt; /* modports here */ endinterface
02

Answer choices (4)