1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ003

Q003DesignDVASIC interview problem

Choose a safe clock-domain crossing strategy

TechniquesCDCMetastabilitySynchronizerHandshake

DifficultyMedium

TopicClock Domain Crossing

LanguageSystemVerilog

Requirements4 checkpoints

Problem

Given a single-bit level, a narrow pulse, a slowly changing multi-bit setting, and a sustained data stream, choose an appropriate clock-domain crossing (CDC) architecture and implement representative single-bit level and pulse synchronizers.

Example input and output

Use this case to check your interpretation

Input

src_clk: a one-cycle event pulse occurs at t=20 ns
dst_clk: unrelated 7 ns period

Output

The destination observes exactly one event after synchronization; no combinational multi-bit sample is used.

Explanation

A pulse toggle or request/acknowledge synchronizer preserves a brief event across unrelated clocks; a two-flop synchronizer alone is only sufficient for a persistent single-bit level.

Requirements (4)

Use a two-flop destination synchronizer only for a stable single-bit level.
Transfer a pulse with an acknowledged toggle; the source may issue a pulse only while src_ready is high.
Use a bundled-data handshake for a held multi-bit value and an asynchronous FIFO for a stream.
Use one shared asynchronous reset event, synchronize its release separately in each domain, and initialize both toggle endpoints to zero.