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DescriptionQ277
Q277DVDesignASIC interview problem

SystemVerilog Assertions (SVA) disable iff

TechniquesSystemVerilogAssertion timing
DifficultyMedium
TopicTemporal Checks
LanguageSystemVerilog
Format4 choices
01

Problem

A request is sampled high, but rst_n goes low before the next edge where gnt would be checked. What happens to that pending assertion attempt?

Starting declarationSystemVerilog
assert property (@(posedge clk) disable iff (!rst_n) req |=> gnt);
02

Answer choices (4)