1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

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DescriptionQ224

Q224DVASIC interview problem

Solve before

TechniquesSystemVerilogAdvanced randomization

DifficultyHard

TopicConstraints

LanguageSystemVerilog

Format4 choices

How does solve a before b change this randomization?

Starting declarationSystemVerilog

rand bit a;
rand bit [1:0] b;
constraint c {
  (a == 0) -> (b == 0);
  solve a before b;
}