Skip to the selected question
ASIC.FYI

ASIC Question Bank

1,000+ hardware interview questions
Question bank1050 results
  1. Easy
  2. Medium
  3. Medium
  4. Easy
  5. Easy
  6. Easy
  7. Easy
  8. Easy
  9. Easy
  10. Easy
  11. Medium
  12. Medium
  13. Hard
  14. Hard
  15. Medium
  16. Medium
  17. Medium
  18. Medium
  19. Medium
  20. Easy
  21. Medium
  22. Easy
  23. Hard
  24. Medium
  25. Hard
  26. Medium
  27. Hard
  28. Medium
  29. Easy
  30. Medium
  31. Medium
  32. Hard
  33. Hard
  34. Medium
  35. Hard
  36. Easy
  37. Medium
  38. Medium
  39. Medium
  40. Hard
  41. Medium
  42. Easy
  43. Medium
  44. Easy
  45. Medium
  46. Medium
  47. Medium
  48. Medium
  49. Medium
  50. Medium
DescriptionQ002
Q002DesignDVASIC interview problem

Build a synchronous FIFO and race-free BFM

TechniquesFIFOBFMClocking blockSimultaneous access
DifficultyMedium
TopicRTL Design
LanguageSystemVerilog
Requirements4 checkpoints
01

Problem

Design a parameterized synchronous FIFO, then write a small bus-functional model that can reset it, push one item, and pop one item without testbench races.

Example input and output

Use this case to check your interpretation
Input
cycle 0: rst_n=0
cycle 1: rst_n=1, push=1, data=0x2A, pop=0
cycle 2: push=1, data=0x7C, pop=1
cycle 3: push=0, pop=1
Output
cycle 0: empty=1, count=0
cycle 1: accept 0x2A, count=1
cycle 2: pop 0x2A and accept 0x7C, count remains 1
cycle 3: pop 0x7C, empty=1, count=0
Explanation

The simultaneous push/pop cycle preserves occupancy, and the race-free BFM samples accepted transfers only on the active clock edge.

02

Requirements (4)

  • Expose full and empty, reject reads while empty, and reject writes while full unless a same-cycle read creates space.
  • Define registered read-data semantics and handle simultaneous accepted reads and writes without corrupting occupancy.
  • Support non-power-of-two depths with explicit pointer wrap logic.
  • Use an interface clocking block so the BFM drives and samples on deterministic scheduler regions.