DescriptionQ184
Q184DVDesignASIC interview problem
SystemVerilog Assertions (SVA) implication
TechniquesSystemVerilogAssertion timing
DifficultyMedium
TopicTemporal Checks
LanguageSystemVerilog
Format4 choices
01
Problem
For the one-cycle antecedent a, which property is cycle-equivalent to the property shown?
Starting declarationSystemVerilog
assert property (@(posedge clk) a |=> b);02