04 · Five independent handshakes
AXI verification must preserve channel independence and transaction dependencies.
AXI separates read address, read data, write address, write data and write response traffic so each channel can stall independently while the transaction remains coherent.
AXI transaction ledger
Independent channel events converge at explicit completion gates.
- 01AWWrite address
Address and attributes transfer whenever AWVALID && AWREADY.
- 02WWrite data beats
Data may arrive before or after AW; accepted WLAST closes the stream.
- 03B gateAW seen ∧ final W seen
The write response becomes eligible only after both dependencies.
- 04BWrite response
BVALID persists independently until BREADY accepts it.
- 05AR → RRead request to beats
An accepted read address creates a response stream ending in RLAST.
Address and attributes transfer whenever AWVALID && AWREADY.
- Channels
- 5
- AW, W, B, AR and R each own a handshake.
- AW versus W
- Either order
- A legal monitor cannot require same-cycle arrival.
- Write completion
- AW + WLAST + B
- The response depends on both accepted request components.
- Stall rule
- Per channel
- VALID and payload persist independently on every channel.
Channel independence improves concurrency but moves complexity into bookkeeping. Verification needs one local handshake checker per channel and one transaction-level model that joins the legal dependencies.
Observe
Record every channel handshake independently, including IDs, attributes, beat counts, LAST and responses.
Decide
Maintain channel-local state plus a transaction ledger that expresses dependencies such as AW accepted and final W accepted before B.
Failure
A design couples AW to W, changes payload under stall, emits B too early or a monitor loses transactions when channels arrive in an unexpected order.
Prove
Bind ready/valid properties to all channels, reconcile channel events in a scoreboard and cover every arrival order, independent stall pattern and outstanding depth.
Give every channel its own monitor state
The five channels use the same ready/valid contract but carry different roles. A robust monitor observes them independently before a transaction assembler or scoreboard joins related events.
| Channel | Direction | Transaction role | Key terminal event |
|---|---|---|---|
| AW | Manager → subordinate | Write address and attributes | AW handshake |
| W | Manager → subordinate | Write data and byte strobes | Accepted WLAST beat |
| B | Subordinate → manager | Write completion response | B handshake |
| AR | Manager → subordinate | Read address and attributes | AR handshake |
| R | Subordinate → manager | Read data and response | Accepted RLAST beat |
Encode the write-response dependency explicitly
For AXI4 and AXI5, a subordinate issues a write response only after the write address and the final write data beat have both been accepted. The example below illustrates one-outstanding bookkeeping; multi-outstanding designs need queues keyed by the architectural association.
- Do not make BVALID combinationally dependent on BREADY.
- Do not infer AW/W order from waveform habit; test W-first, AW-first and simultaneous acceptance.
- This one-outstanding ledger must reject a second AW, a second terminal W beat, or same-cycle response turnover unless the implementation explicitly adds queueing for those cases.
- AXI4 removed WID and write-data interleaving. Write-data bursts remain associated in AW transaction order even though an individual W burst may begin before its AW handshake.
- A multi-outstanding checker can keep ordered AW and completed-W-burst queues, then join their fronts; independent channel timing does not permit arbitrary address/data pairing.
always_ff @(posedge ACLK or negedge ARESETn) begin
if (!ARESETn) begin
aw_seen <= 1'b0;
wlast_seen <= 1'b0;
end else begin
if (AWVALID && AWREADY) aw_seen <= 1'b1;
if (WVALID && WREADY && WLAST)
wlast_seen <= 1'b1;
if (BVALID && BREADY) begin
aw_seen <= 1'b0;
wlast_seen <= 1'b0;
end
end
end
assert property (@(posedge ACLK) disable iff (!ARESETn)
BVALID |-> aw_seen && wlast_seen);
assert property (@(posedge ACLK) disable iff (!ARESETn)
AWVALID && AWREADY |-> !aw_seen);
assert property (@(posedge ACLK) disable iff (!ARESETn)
WVALID && WREADY && WLAST |-> !wlast_seen);
assert property (@(posedge ACLK) disable iff (!ARESETn)
BVALID && !BREADY |=> BVALID && $stable(BRESP));Use reset to terminate protocol obligations deliberately
Reset clears interface VALID state and local channel trackers, but a system-level environment must also decide what happens to already accepted work beyond the reset boundary.
- Flush or epoch-tag expected transactions according to the architectural reset scope.
- Reject unmatched late responses rather than allowing them to alias a newly reused ID.
- Randomize reset during every channel stall and between dependent write events.
- After release, verify all output VALID signals start from the required reset state before new traffic begins.
Explain it out loud
Interview reasoning checkpoints
No. AW and W are independent channels, so write data may be accepted before, after or with the write address.
- Each channel has its own VALID/READY handshake.
- A subordinate or interconnect retains enough state to associate the accepted components legally.
- The write response waits for both the address and the final data beat.
This exposes testbenches that accidentally constrain AXI into a simpler same-cycle protocol.
Writing a monitor or slave driver that ignores WVALID until AW has already handshaken.
No. As the response source, it asserts BVALID when the response is available and holds it until BREADY accepts it.
- VALID ownership always belongs to the source of that channel.
- Waiting for READY can create a circular dependency.
- BRESP must remain stable while BVALID is stalled.
The question checks whether the candidate applies the same handshake rule consistently in the reverse direction.
Remembering the manager-side VALID rules but treating response channels as special.
Channel monitors preserve independent handshake truth, while the transaction scoreboard joins those events using AXI’s explicit dependencies, IDs and beat rules.
- Local monitors can report payload stability and channel timing precisely.
- A transaction assembler can tolerate legal channel reordering.
- The scoreboard remains focused on end-to-end data, response and ordering correctness.
This tests verification architecture, not only protocol memorization.
One monolithic monitor that assumes a fixed AW/W/B sequence and silently misses unusual but legal timing.