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Part 3 · Probability and debug

Count legal solutions, predict stimulus bias, preserve failing seeds, and reduce empty solution spaces without obscuring the original intent.

Question directory

Questions for Probability + debug

Open an authored answer, then use the surrounding visual and code example to test the rule.

  1. Solver probabilityGiven type_a -> val == 3, what is the probability that type_a is 1?SystemVerilog constraints
  2. Solver probabilityHow does an inline range restriction change an existing dist constraint?SystemVerilog constraints
  3. Solver probabilityHow do constraint probabilities affect coverage closure time?SystemVerilog constraints
  4. Patterns and solver debugHow would you generate valid parity most of the time but occasionally inject an error?SystemVerilog constraints
  5. Patterns and solver debugHow would you constrain sorted, non-overlapping time windows with a minimum gap?SystemVerilog constraints
  6. Patterns and solver debugHow do you debug a randomize() failure and reproduce it?SystemVerilog constraints
  7. Solver probabilityWhy is FAST selected 7/11 of the time in a mode-and-length model?SystemVerilog constraints
  8. Solver probabilityIf a scenario has probability 1/11, how many hits should 100 tests produce?SystemVerilog constraints
  9. Patterns and solver debugHow do you couple packet length, payload size, opcode rules, and an even byte sum?SystemVerilog constraints
  10. Patterns and solver debugHow do you demonstrate an intentional inline-constraint failure and a valid recovery?SystemVerilog constraints
  11. Patterns and solver debugHow do process and object reseeding affect reproducibility?SystemVerilog constraints
  12. Patterns and solver debugWhat makes a constraint model maintainable and solver-friendly?SystemVerilog constraints

SystemVerilog Solver probabilityCount solutions before predicting traffic.

Explain how legal-pair counts, solve before, weighted ranges, and rare events affect the stimulus distribution and the time required to reach coverage.

Concept model

Solve ordering changes sampling, not legality

Same legal solution setThree SHORT lengths, twelve LONG lengths
kind == SHORT -> length inside {[1:3]};
kind == LONG  -> length inside {[4:15]};
Marginal distributionSample complete pairs

Sample complete legal pairs. LONG owns twelve pairs while SHORT owns three, so LONG is selected four times as often. All fifteen legal pairs remain available.

Both modes preserve the same legal pairs. Default sampling favors values with more compatible partners, while solve before chooses the ordered variable first.

SystemVerilog Patterns and solver debugMake failures small and reproducible.

Use hooks for procedural derivation, write structured collection problems clearly, and isolate an empty solution space without discarding the failing seed.

Concept model

Reconstruct the failure before changing the model

Failure evidenceReconstruct the exact model that returned zero
Seed and identitytest seed · object type · instanceProve you are replaying the same experiment.
Fixed object staterand_mode() · non-rand valuesFrozen values still participate in active rules.
Active modelclass · inherited · inline · modesHard rules intersect; incompatible soft rules yield.
Observed resultrandomize() == 0

The active hard relationships share no assignment.

Progressive isolationChange one thing, then preserve the evidence
  1. 01Confirm failurecheck the return bit
  2. 02Freeze the scenerecord state + modes
  3. 03Reduce the modeldisable one named block
  4. 04Prove the conflictre-enable one block at a time
rand_mode(0) freezes a variable; it does not remove its value from active constraints.A disabled block may reveal the conflict, but the requirement still needs a specification-backed repair.

Preserve the seed, object identity, fixed state, and active modes. Then reduce the model one named block at a time until the empty intersection is explainable.