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UVM objection ownership

EasyUVMSystemVerilog

A run_phase starts a finite stimulus sequence and the test must not end until that sequence completes. Where should the objection normally be raised and dropped?

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Answer choices

  1. A. Never use an objection; run_phase automatically waits for every sequence object that was constructed.
  2. B. Raise in build_phase and drop in final_phase because those phases surround the whole test.
  3. C. Raise before starting the sequence and drop after the sequence returns, using the same phase objection.
  4. D. Raise after the sequence returns and drop immediately before starting it.
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