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Hardware interview practice

Synchronous rising-edge detector

EasySequential RTLSystemVerilog

Write synthesizable SystemVerilog that produces one clock-cycle pulse when a clock-synchronous input changes from 0 to 1. If the source is asynchronous, it must be synchronized before this block.

Starting point

Question code

module rise_detector (
  input  logic clk,
  input  logic rst_n,
  input  logic in_sync,
  output logic rise_pulse
);
Reviewed example

Work through one case

Input
sampled in_sync = 0, 0, 1, 1, 0, 1
Expected output
rise_pulse = 0, 0, 1, 0, 0, 1

A pulse is generated only when the current sample is high and the stored previous sample is low.

What to cover

Requirements

  1. Sample in_sync only on rising clock edges.
  2. Reset the stored history and pulse output to zero.
  3. A signal held high for multiple clocks produces one pulse only.
  4. Do not create a combinational asynchronous path from the input to rise_pulse.
Continue practicing
RTL DesignCombinational versus sequential logic