Hardware interview practice
Separate Pipeline Frequency, Throughput, and Latency
An unpipelined function has 12 ns of combinational delay and accepts a new item only after the current result. Two register boundaries split it into three balanced 4 ns stages. Register overhead is ignored for this exercise. Which performance statement is correct?
Choose one
Answer choices
- A. The pipelined version can use a 4 ns clock, has three-cycle latency from input to output, and after filling can complete one item per cycle if control and data are aligned.
- B. The pipelined version has 4 ns total input-to-output latency because its clock period is 4 ns.
- C. The pipelined version completes three independent items every clock because it has three stages.
- D. Pipelining reduces the arithmetic work per item and therefore must reduce dynamic power.