Skip to question
asic.fyi
DesignVerificationSystemVerilogFirmwareArchitectureInterviews
asic.fyi/Interview questions/Rotate a packed word

Hardware interview practice

Rotate a packed word

MediumBit ManipulationSystemVerilog

Implement rotate-left and rotate-right for a W-bit packed vector.

Try it in the question bankReason first. Then compare.

Keep this exact question selected while you check your answer and review the full solution.

Practice this question →
Reviewed example

Work through one case

Input
W=8, word = 8'b1001_0001, rotate_left = 3
Expected output
8'b1000_1100

The upper three bits wrap into the low end rather than being discarded.

What to cover

Requirements

  1. Require W to be a positive compile-time width.
  2. Normalize shifts larger than W.
  3. Return x unchanged when the normalized shift is zero.
  4. Do not accidentally perform a shift by W.
Continue practicing

Related questions

Bit ManipulationReverse a bit vector→
asic.fyi · Learn silicon end to end.info@asic.fyi