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Hardware interview practice

Reverse a bit vector

EasyBit ManipulationSystemVerilog

Reverse the bit order of a W-bit vector.

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Reviewed example

Work through one case

Input
W=8, value = 8'b1101_0010
Expected output
8'b0100_1011

Output bit i receives input bit 7-i, including the leading and trailing zeros.

What to cover

Requirements

  1. Support a compile-time width parameter.
  2. Map input bit W - 1 - i to output bit i.
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