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Hardware interview practice

Review and scope false-path candidates

MediumClock and Reset DomainsSystemVerilog

Perform a functional-mode exception review for the three paths below; scan_mode is fixed to zero in this analysis view. Design the path classification, SDC action, and audit checks.

Starting point

Question code

A: config_reg/Q -> data_reg/D; active functional path
B: scan_in -> scan_mux -> data_reg/D; selected only when scan_mode=1
C: async_irq -> sync1/D -> sync2/D; unrelated source
functional view: set_case_analysis 0 on scan_mode
Reviewed example

Work through one case

Input
Case 1: Path A reports -100 ps setup slack
Case 2: Apply set_case_analysis 0 to scan_mode
Case 3: Cut async_irq to sync1/D for path C
Expected output
Case 1: keep it in setup and hold analysis; fix the path or change the functional specification
Case 2: the scan branch is inactive in the functional analysis view
Case 3: sync1/Q to sync2/D still receives ordinary destination-clock timing

The shown result follows by applying this rule: Require structural or protocol proof that a path cannot be sensitized/captured before applying an exception. The cases also demonstrate this requirement: Audit exception coverage, CDC structure, case-analysis propagation, and unconstrained paths; reject a blanket false path to all data_reg or synchronizer endpoints.

What to cover

Requirements

  1. Keep A normally timed; its failing slack is a real functional timing problem, not an exception candidate.
  2. Disable B in the functional view with the stated case analysis; if a residual path remains, false-path only the exact inactive scan branch and verify it is unreachable.
  3. Exclude only the asynchronous source-to-sync1 setup/hold relationship for C, mark the synchronizer, and keep sync1/Q-to-sync2/D normally timed.
  4. Audit exception coverage, CDC structure, case-analysis propagation, and unconstrained paths; reject a blanket false path to all data_reg or synchronizer endpoints.
Continue practicing
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