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Hardware interview practice

Compare transactions with useful messages

EasyVerification UtilitiesSystemVerilog

Compare expected and actual transactions. Return an empty string when they match, otherwise return a human-readable list of mismatched fields.

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Reviewed example

Work through one case

Input
expected=(id=7,addr=0x10,data=16'hA5XZ); actual=(id=8,addr=0x14,data=16'hA5X1)
Expected output
message reports mismatches for id, addr, and data

The comparator accumulates all three field mismatches and uses case inequality so a four-state data difference is not hidden.

What to cover

Requirements

  1. Report every mismatch, not just the first.
  2. Use case inequality to expose X or Z differences.
  3. Include expected and actual values.
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