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Hardware interview practice

Latch versus flip-flop behavior

EasyTimingSystemVerilog

Which statement distinguishes a level-sensitive latch from an edge-triggered flip-flop?

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Answer choices

  1. A. A latch is transparent during its active level; a flip-flop samples at an active edge
  2. B. A latch has no setup or hold requirement
  3. C. A flip-flop is transparent for half a cycle
  4. D. A latch can store only one logic value
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