Hardware interview practice

Delayed nonblocking assignments

HardSystemVerilogSystemVerilog

Which transition history for a is correct?

Starting point

Question code

int a = 0;
initial begin
  #1 a <= #5 1;
  #2 a <= #2 2;
end

Choose one

A. a becomes 2 at time 5 and then 1 at time 6
B. a becomes 1 at time 6 and then 2 at time 10 because each intra-assignment delay blocks the process
C. a becomes only 2 at time 5 because the later statement cancels the first
D. a becomes 1 at time 8 and never becomes 2

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