Skip to question
asic.fyi

Hardware interview practice

Implement a coordinated-reset depth-16 asynchronous FIFO

HardClock and Reset DomainsSystemVerilog

Build a 32-bit, depth-16 dual-clock FIFO. System reset asserts both domain reset pins for a flush; release is synchronized separately, and each side exchanges a synchronized domain-up indication before transfers begin. For this exercise, the dual-port storage supports an asynchronous first-word-fall-through read. Implement the asynchronous FIFO and its safety assertions.

Starting point

Question code

write: wclk,wrst_n,w_valid,w_ready,w_data[31:0],w_full
read: rclk,rrst_n,r_valid,r_ready,r_data[31:0],r_empty
capacity: 16 accepted words; coordinated reset flush only
internal: local domain_up bits, each synchronized into the other domain
read mode: asynchronous first-word-fall-through at current read address
Reviewed example

Work through one case

Input
Case 1: Accept sixteen writes without any reads
Case 2: Perform one read from a full FIFO
Case 3: Apply a coordinated reset with queued data
Expected output
Case 1: after the sixteenth pointer advance, w_ready=0 and w_full=1
Case 2: w_full may stay high until the read Gray pointer synchronizes, and no write is accepted while full
Case 3: discard the data; return with empty/reset flags and zero pointers, then restore readiness only after both up indications cross

The shown result follows by applying this rule: Use the standard local-binary/local-Gray architecture, dual-port storage, and two-flop synchronization for Gray pointers and remote domain-up indications. The cases also demonstrate this requirement: Force r_valid=0,r_empty=1,w_ready=0,w_full=0 until both sides are up. Once active, drive r_valid from not-empty and r_data from the current read address; a stall holds the read pointer and therefore data stable. Coordinated reset flushes state; assert against overflow, underflow, pointer jumps, and one-sided live reset.

What to cover

Requirements

  1. Use five-bit local binary pointers with four-bit memory addresses, and update a pointer only on its local accepted transfer. Set w_ready only when both synchronized domain-up conditions are true and w_full is false.
  2. Register local Gray pointers and pass each through two destination-domain synchronizer stages; raise each local domain-up bit only after local synchronized reset release, synchronize it into the other domain, and never synchronize binary pointers bit by bit.
  3. Generate registered empty from next read Gray equaling synchronized write Gray and full from next write Gray equaling synchronized read Gray with its top two bits inverted.
  4. Force r_valid=0,r_empty=1,w_ready=0,w_full=0 until both sides are up. Once active, drive r_valid from not-empty and r_data from the current read address; a stall holds the read pointer and therefore data stable. Coordinated reset flushes state; assert against overflow, underflow, pointer jumps, and one-sided live reset.
Continue practicing
Clock and Reset DomainsIdentify an asynchronous-reset recovery violationClock and Reset DomainsImplement a deterministic true dual-port RAMCDC and ResetCheck reset-bounded delivery of asynchronous events