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Hardware interview practice

Generate ordered-signature matches

HardConstraintsSystemVerilog

Write an ordered-subsequence oracle, a legal-by-construction positive generator, and coverage points for a trace checker whose short event pattern must occur in order within a longer frame.

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Reviewed example

Work through one case

Input
pattern=[3,7,3]; events=[1,3,5,7,9,3,12]
Expected output
matched=1 using event positions [1,3,5]

Gaps are legal in an ordered subsequence, and the repeated value 3 is consumed at two distinct increasing positions.

What to cover

Requirements

  1. Advance the oracle's pattern index only when an accepted event equals the next required code; an empty pattern matches every legal frame.
  2. Construct positive cases by choosing increasing embedding positions and filling the gaps independently.
  3. After deleting an occurrence or changing order to make a negative candidate, label it negative only when the oracle confirms nonmatch.
  4. Predict request_error and matched=0 when pattern_len exceeds 8 or event_len exceeds 32.
  5. Cover repeated codes, gap size, match location, and the cause used to construct a confirmed negative.
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