Skip to question
asic.fyi
DesignVerificationSystemVerilogFirmwareArchitectureInterviews
asic.fyi/Interview questions/Generate opcode-bijection stimulus

Hardware interview practice

Generate opcode-bijection stimulus

HardConstraintsSystemVerilog

Write an oracle and compact stimulus constructors for a checker that decides whether two opcode traces use one consistent one-to-one renaming.

Try it in the question bankReason first. Then compare.

Keep this exact question selected while you check your answer and review the full solution.

Practice this question →
Reviewed example

Work through one case

Input
len_a=len_b=4; trace A=[1,2,1,0]; trace B=[9,6,9,4]
Expected output
request_error=0; cause=ISO_OK; isomorphic=1

The consistent one-to-one renaming is 1->9, 2->6, and 0->4. Repeated source opcode 1 maps to 9 both times, and no destination is shared by two sources.

What to cover

Requirements

  1. Construct positive traces from a one-to-one mapping of only the source symbols actually used.
  2. Provide one exact constructor each for unequal length, forward conflict, and reverse conflict.
  3. Use fresh forward and reverse valid/value tables for every oracle call and ignore inactive suffix entries.
  4. Treat either length above 16 as request_error and zero the functional result.
  5. Identify length, repeated-symbol presence, opcode-zero participation, expected cause, and result as follow-up coverage dimensions.
Continue practicing

Related questions

ConstraintsConstrain and cover an ASCII palindrome checker→ConstraintsGenerate ordered-signature matches→Verification UtilitiesRegress cross-transaction histogram leakage→
asic.fyi · Learn silicon end to end.info@asic.fyi