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Hardware interview practice

Generate a temporal hazard-safe instruction stream

HardConstraintsSystemVerilog

Randomize an instruction stream whose current instruction obeys dependencies on the previous two instructions, while guaranteeing that at least 20 percent of the complete stream consists of LOAD operations.

Reviewed example

Work through one case

Input
randomize N=5 instructions using {ADD,MUL,DIV,LOAD}
Expected output
One valid result: LOAD r1,r2->r3; ADD r4,r5->r6; DIV r7,r8->r9; MUL r10,r11->r12; LOAD r13,r14->r15

Two LOADs exceed the required ceil(5/5)=1. Each destination avoids the prior two instructions' sources, and DIV sources r7/r8 avoid prior destinations r3/r6; many other streams are valid.

What to cover

Requirements

  1. For DIV, neither source may equal either of the previous two destination registers.
  2. Every new destination must differ from both source registers of each of the previous two instructions.
  3. The finite stream must contain at least ceil(N/5) LOADs; probabilistic weighting alone is insufficient.
  4. Apply only the history constraints that exist at indices zero and one.
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