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Hardware interview practice

Constrain a DMA transfer to one 4KB page

MediumConstraintsSystemVerilog

Constrain a randomized DMA transaction with a 64-bit address, a 64-to-4096-byte length in 64-byte units, and LINEAR or FIXED burst type. Incrementing transfers may not cross a 4KB page.

Reviewed example

Work through one case

Input
burst_type=LINEAR, 4 KiB page size, length_bytes=128
Expected output
One valid randomized result: addr=0x1803, final_byte=0x1882

Both endpoints lie in page 0x1000..0x1FFF. Alignment is not part of this question, so any other start that stays inside the page is also legal.

What to cover

Requirements

  1. Length must be within 64 through 4096 bytes and divisible by 64.
  2. For LINEAR bursts, the last byte must remain in the same 4KB page as the first byte.
  3. A FIXED burst may contain at most 256 bytes.
  4. Allow a 4096-byte LINEAR transfer only when the start address is page aligned.
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