Hardware interview practice
Flag unknown outputs after reset
A gate-level simulation may briefly contain unknown values after reset release, but a 16-bit output must be fully known after a two-cycle settling allowance. Write a SystemVerilog checker for the reset and unknown-value contract.
Starting point
Question code
input logic clk, rst_n;
input logic [15:0] data_out;
output logic check_enable;Reviewed example
Work through one case
Input
Release reset before C1 and keep data_out fully known through C1, C2, and C3.Expected output
C1 and C2 are untested settling edges; checking is enabled at C3 and no assertion fails.The two-edge counter enables the unknown-value check only after both allowed settling samples have elapsed.
What to cover
Requirements
- When rst_n=0 at a rising edge, clear a two-cycle release counter and check_enable.
- After rst_n is sampled high on two consecutive rising edges, set check_enable and keep it high until reset.
- On every later rising edge with check_enable=1, assert that !$isunknown(data_out).
- Do not check data_out on either of the two settling edges; a reset assertion immediately disables future checks at that sampled edge.