Hardware interview practice

Design glitch-free clock gating

MediumLow-Power DesignSystemVerilog

Describe a glitch-free positive-edge clock-gating implementation and the checks that prove it cannot create runt pulses.

Starting point

Question code

input logic clk, rst_n, en;
output logic gclk;

Reviewed example

Input

en falls while clk is high and the current gclk pulse is active

Expected output

The active gclk pulse completes; gating stops at the next safe low phase

The stored gate enable cannot change during the propagated high pulse.

What to cover

Capture the functional enable only while clk is low, using an approved ICG or an equivalent low-phase model.
Allow a propagated high pulse to complete even if en changes while clk is high.
Treat reset/test disable through the library-approved safe control path; do not asynchronously truncate gclk high.
Check source-edge alignment, pulse width, enable stability during high phase, and no gated edge while disabled.

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