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Hardware interview practice

Design a four-request arbiter verification environment

HardArbitersSystemVerilog

Design end-to-end verification for four one-cycle request inputs where simultaneous requests use lower-index priority and grants are ordered, one-hot, and held for 1 through 10 cycles.

Starting point

Question code

input logic clk, rst_n;
input logic [3:0] req;
input logic [3:0] grant;
Reviewed example

Work through one case

Input
req = 4'b1010 together; then grant = 4'b0010 for four cycles
Expected output
enqueue requester 1 then requester 3; complete one legal service for requester 1

Low-index priority defines the model's insertion order, and the one-hot grant matches the queue front for an allowed duration.

What to cover

Requirements

  1. Define how simultaneous request bits enter the pending model.
  2. Separate driver, passive monitor, scoreboard, assertions, and coverage responsibilities.
  3. Check one-hot grant, a pending requester, stable service, and duration 1 through 10.
  4. Cover requesters, multi-hot arrivals, wait latency, service duration, and back-to-back grants.
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