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Hardware interview practice

Default sequences

MediumUVM ComponentsSystemVerilog

Which UVM 1.2-style configuration installs my_seq by type as the default sequence for seqr's main_phase?

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Answer choices

  1. A. uvm_config_db#(uvm_object_wrapper)::set(this, "env.agt.seqr.main_phase", "default_sequence", my_seq::type_id::get());
  2. B. uvm_config_db#(int)::set(this, "env.agt", "default_sequence", my_seq::get_type_name());
  3. C. uvm_factory::get().set_type_override_by_name("main_phase", "my_seq");
  4. D. seqr.seq_item_export.connect(my_seq.default_sequence);
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