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Hardware interview practice

Constrain a bounded packet split

MediumSystemVerilog & UVMSystemVerilog

A transfer is divided into a fixed number of random packet lengths while leaving enough bytes for every remaining packet. Write a SystemVerilog constraint class for the packet lengths.

Starting point

Question code

class packet_split;
rand int unsigned len[8];
int unsigned total, count, min_len, max_len;
constraint legal_c;
endclass
Reviewed example

Work through one case

Input
total=12, count=3, min_len=4, and max_len=4.
Expected output
The only legal randomized array is {4,4,4,0,0,0,0,0}.

Three active entries must each equal four and sum to twelve, while every inactive entry is constrained to zero.

What to cover

Requirements

  1. randomize() is legal only when 1<=count<=8, max_len<=65535, min_len<=max_len, total<=65535, and count*min_len<=total<=count*max_len.
  2. For every active i<count, require min_len<=len[i]<=max_len and the sum of active lengths to equal total.
  3. Set every inactive len[i] for i>=count to zero.
  4. Add ordering or solve-before constraints only if needed for solver clarity; do not use post_randomize to repair an illegal result.
Continue practicing
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