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Concurrent assertion scheduling

EasySystemVerilogSystemVerilog

At a clock event, where are values used by a concurrent assertion normally sampled and where is the property evaluated?

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assert property (@(posedge clk) req |-> gnt);
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Answer choices

  1. A. Sampled in Active, evaluated in NBA
  2. B. Both sampled and evaluated in Reactive
  3. C. Sampled in NBA, evaluated in Postponed
  4. D. Sampled in Preponed, evaluated in Observed
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