Skip to question
asic.fyi
DesignVerificationSystemVerilogFirmwareArchitectureInterviews
asic.fyi/Interview questions/Choose AXI or APB for a control block

Hardware interview practice

Choose AXI or APB for a control block

EasyProtocols and InterfacesSystemVerilog

A low-rate register block accepts one request at a time, supports no bursts, and should use little interface logic. Which on-chip interface is the best fit?

Try it in the question bankReason first. Then compare.

Keep this exact question selected while you check your answer and review the full solution.

Practice this question →
Choose one

Answer choices

  1. A. AXI-Stream, because register reads do not need an address.
  2. B. Full AXI, because bursts and multiple outstanding IDs reduce control-block logic.
  3. C. APB, because its simple two-phase, non-pipelined transfer matches low-bandwidth register access.
  4. D. AXI-Lite, because a five-channel interface is always smaller than APB.
Continue practicing

Related questions

Design VerificationDistinguish AXI-Lite from AXI3→
asic.fyi · Learn silicon end to end.info@asic.fyi