DFT, Physical Design,and Signoff InterviewQuestions You Should Master

A complete handoff includes the design database, the constraints and intent used to interpret it, and evidence that the producing stage met an agreed acceptance contract.

DFT architecture starts before synthesis, scan insertion usually operates on a synthesized test-ready netlist, and its added clocks, modes, chains, and timing paths remain part of physical implementation and signoff.

Routing creates geometry, but tapeout requires extracted electrical analysis, manufacturing-rule checks, connectivity agreement, reliability checks, and proof that late implementation changes preserved logic.

Shift mode connects scan flops as serial chains to load and unload state. Capture mode restores the functional data paths so one or more controlled clock edges record the circuit response.

ATPG drives the fault site to the opposite of the faulty value, chooses side inputs that sensitize a path, and propagates the resulting difference to a scan cell or observable output.

A transition test launches a value change and captures its arrival using the functional-speed edge spacing, so excessive path delay can be observed as an incorrect sampled value.

An unknown entering a linear compactor can contaminate many signature bits and hide otherwise deterministic fault effects, so known X sources need masking, blocking, control, or bypass before compaction.

A March test applies ordered read and write operations while traversing addresses in specified directions, creating the background and neighbor activity needed to expose cell, transition, address, and coupling faults.

Scan and ATPG target random logic, MBIST applies memory-specific algorithms, and JTAG or an embedded-instrument network provides external access and selection. A chip test controller coordinates shared clocks, resets, modes, and status.

A routable floorplan gives high-connectivity regions enough tracks, pin access, vias, and detour options after accounting for macros, halos, blockages, the power grid, and clock resources.

Utilization measures placed-cell area over a region, while congestion compares routing demand with local track and via capacity. Macros, pins, blockages, and directional traffic can exhaust capacity even when cell area is modest.

CTS builds a clock network that reaches every sink within transition, capacitance, latency, skew, routing, and power limits across required scenarios. The best tree is the one that supports full-path timing, not necessarily the one with minimum skew.

A long route accumulates distributed resistance and capacitance, while coupling capacitance changes the effective load according to relative aggressor and victim switching. Opposite-direction transitions usually slow the victim more than quiet or same-direction neighbors.

IR drop limits the voltage lost through resistive paths at required current, while electromigration limits current density in wires and vias. Strap and via sizing must satisfy both constraints in every required activity scenario.

During fabrication, charge collected on a partially formed conductor can stress a connected gate oxide before a safe discharge path exists. Antenna rules bound exposed conductor area relative to vulnerable gate area for each process stage.

Setup checks a maximum-delay path against a later capture boundary, while hold checks a minimum-delay path against the current boundary. Speeding data helps setup but can hurt hold; delaying data helps hold but can consume setup margin.

Skew changes the relative launch and capture arrivals, uncertainty reserves margin for unmodeled clock variation, OCV derates model different path behavior, and CRPR removes impossible double counting on shared clock segments.

An exception is valid only when it describes a real architectural sampling relationship: a false path is never functionally captured, a multicycle path is intentionally captured on a later edge, and clock groups declare defined clock relationships or their absence.

MMMC closure means every required analysis view meets its acceptance criteria on the same releasable design, with modes, clocks, parasitics, libraries, voltage, process, temperature, derates, and exceptions configured consistently.

First confirm the violation and its model, then choose a localized root-cause fix, run fast incremental analysis, and finally reestablish full timing, physical, power, and equivalence signoff on the updated database.

STA checks declared timing relationships, SI checks coupling effects, IR and EM check power delivery and conductor reliability, DRC checks geometry, LVS checks connectivity, and equivalence checks logical consistency with the reference.