Hardware interview practice
Verify a four-lane PCIe deskew buffer
Four lanes carry numbered symbols. A lane may lag the leader by at most seven symbol-times. Build a reference model and test plan for aligned output, overflow detection, backpressure, reset, and recovery.
Reviewed example
Work through one case
Input
Symbol 42 arrives in lane slots [100,103,107,101]; later symbol 99 arrives with slots [200,208,203,201]Expected output
Symbol 42 emits once after slot 107 because skew=7. Symbol 99 causes deskew_error because skew=8; no group 99 emits, queues flush, and output stays blocked until a common recovery marker.Skew is measured in per-lane symbol-transfer opportunities, not raw simulator time or byte count, and the recovery contract prevents stale pre-error symbols from leaking out.
What to cover
Requirements
- Define one symbol-time as one opportunity for a lane to transfer a valid symbol. For a particular symbol k, skew is max(arrival_slot[k,lane]) minus min(arrival_slot[k,lane]) across the four lanes.
- Preserve order within each lane and emit group k only when symbol k is at the head of all four lane queues; skew 0..7 must produce one lossless aligned group.
- When observed skew reaches 8, assert deskew_error, emit no corrupted group, flush partial lane queues, and enter recovery.
- Leave recovery only after reset/retrain or an explicit alignment marker observed on every lane; then restart from the following common symbol. Test gaps, backpressure, leader changes, skew boundaries, reset mid-packet, error, and recovery.