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UVM checker for register retention

HardLow PowerSystemVerilog

A power island contains 32 registers. A fixed mask marks registers that must retain their values across power-down. Write UVM checker methods for the power transition and register observations.

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Starting point

Question code

function void observe_reg(int unsigned a, bit [31:0] v);
function void power_down();
function void power_up();
function void reset_seen();
bit [31:0] retain_mask;
Reviewed example

Work through one case

Input
retain_mask has only bit3 set; observe_reg(3,0x55), power_down(), power_up(), then observe_reg(3,0x55).
Expected output
No error is added, pending becomes zero, state returns to AWAKE, and seen clears.

Register 3 was observed before sleep, snapshotted, and matched exactly once during VERIFY.

What to cover

Requirements

  1. Track explicit AWAKE, POWERED_DOWN, and VERIFY states. Addresses above 31 report an error in every state. In AWAKE, observe_reg records legal addresses and marks them seen; in POWERED_DOWN, any observe_reg call reports an error and changes no state.
  2. power_down is legal only in AWAKE after every retained address was seen; snapshot retained values and enter POWERED_DOWN. A missing observation or wrong-state call reports an error and changes no state.
  3. power_up is legal only in POWERED_DOWN; enter VERIFY with pending=retain_mask, or clear seen and return directly to AWAKE when the mask is zero. In VERIFY, a pending retained observation compares once and clears its bit even on mismatch; an already-checked retained address is an error, a nonretained address is ignored, and clearing the final pending bit returns AWAKE with seen=0.
  4. reset_seen from any state clears values, seen bits, snapshots, pending bits, and errors for a new epoch, then enters AWAKE. check_phase reports an error unless state is AWAKE and pending is zero.
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