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Use Wildcard Case Constructs without Hiding Unknowns

MediumDesign VerificationSystemVerilog

A control decoder receives `sel = 2'bx1`. Its source code uses `casex (sel)` with an item `2'b01`, so simulation may select that item even though the high bit is unknown. Which explanation and remedy are correct?

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Answer choices

  1. A. Replace the decoder with case equality `===`; that automatically synthesizes a priority decoder and removes all X values from hardware.
  2. B. `casex` treats only Z as a wildcard, so the item cannot match while `sel[1]` is X.
  3. C. Ordinary `case` also treats X as a wildcard, so changing constructs cannot affect the result.
  4. D. `casex` treats X and Z bits as wildcards in both the expression and items, so it can hide a real unknown; use explicit masks or `case inside`/careful `casez` plus assertions that required control bits are known.
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