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Hardware interview practice

Resolve a read-and-clear counter race

MediumRTL DesignSystemVerilog

A packet block accumulates byte counts. Firmware can read and clear the count while a packet completion arrives on the same edge. Implement the counter with explicit simultaneous behavior.

Starting point

Question code

input logic clk, rst_n;
input logic event_valid;
input logic [15:0] event_bytes;
input logic rd_en;
output logic [31:0] rd_data;
output logic [31:0] live_count;
Reviewed example

Work through one case

Input
live_count=7, rd_en=1, event_valid=1, event_bytes=3
Expected output
rd_data=7; live_count=3

Firmware receives the pre-edge count while the simultaneous event starts the next accumulation window.

What to cover

Requirements

  1. Reset is synchronous active-low and sets rd_data and live_count to zero.
  2. An event adds event_bytes to live_count with modulo-2^32 arithmetic.
  3. On rd_en, copy the pre-edge live_count into rd_data and clear that old count.
  4. If rd_en and event_valid are both 1, rd_data receives the pre-edge count and the new event becomes the new live_count.